Executive Summary



This vulnerability is currently undergoing analysis and not all information is available. Please check back soon to view the completed vulnerability summary
Informations
Name CVE-2025-45006 First vendor Publication 2025-07-01
Vendor Cve Last vendor Modification 2025-07-01

Security-Database Scoring CVSS v3

Cvss vector : N/A
Overall CVSS Score NA
Base Score NA Environmental Score NA
impact SubScore NA Temporal Score NA
Exploitabality Sub Score NA
 
Calculate full CVSS 3.0 Vectors scores

Security-Database Scoring CVSS v2

Cvss vector :
Cvss Base Score N/A Attack Range N/A
Cvss Impact Score N/A Attack Complexity N/A
Cvss Expoit Score N/A Authentication N/A
Calculate full CVSS 2.0 Vectors scores

Detail

Improper mstatus.SUM bit retention (non-zero) in Open-Source RISC-V Processor commit f517abb violates privileged spec constraints, enabling potential physical memory access attacks.

Original Source

Url : http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2025-45006

Sources (Detail)

https://github.com/chipsalliance/rocket-chip.git
https://github.com/heyfenny/Vulnerability_disclosure/blob/main/RISCV/Rocket-c...
https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154769/RISC-V+Technic...
Source Url

Alert History

If you want to see full details history, please login or register.
0
Date Informations
2025-07-02 00:21:16
  • First insertion