Executive Summary

Informations
Name CVE-2021-47226 First vendor Publication 2024-05-21
Vendor Cve Last vendor Modification 2025-04-29

Security-Database Scoring CVSS v3

Cvss vector : CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:N/I:H/A:H
Overall CVSS Score 7.1
Base Score 7.1 Environmental Score 7.1
impact SubScore 5.2 Temporal Score 7.1
Exploitabality Sub Score 1.8
 
Attack Vector Local Attack Complexity Low
Privileges Required Low User Interaction None
Scope Unchanged Confidentiality Impact None
Integrity Impact High Availability Impact High
Calculate full CVSS 3.0 Vectors scores

Security-Database Scoring CVSS v2

Cvss vector :
Cvss Base Score N/A Attack Range N/A
Cvss Impact Score N/A Attack Complexity N/A
Cvss Expoit Score N/A Authentication N/A
Calculate full CVSS 2.0 Vectors scores

Detail

In the Linux kernel, the following vulnerability has been resolved:

x86/fpu: Invalidate FPU state after a failed XRSTOR from a user buffer

Both Intel and AMD consider it to be architecturally valid for XRSTOR to fail with #PF but nonetheless change the register state. The actual conditions under which this might occur are unclear [1], but it seems plausible that this might be triggered if one sibling thread unmaps a page and invalidates the shared TLB while another sibling thread is executing XRSTOR on the page in question.

__fpu__restore_sig() can execute XRSTOR while the hardware registers are preserved on behalf of a different victim task (using the fpu_fpregs_owner_ctx mechanism), and, in theory, XRSTOR could fail but modify the registers.

If this happens, then there is a window in which __fpu__restore_sig() could schedule out and the victim task could schedule back in without reloading its own FPU registers. This would result in part of the FPU state that __fpu__restore_sig() was attempting to load leaking into the victim task's user-visible state.

Invalidate preserved FPU registers on XRSTOR failure to prevent this situation from corrupting any state.

[1] Frequent readers of the errata lists might imagine "complex
microarchitectural conditions".

Original Source

Url : http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2021-47226

CWE : Common Weakness Enumeration

% Id Name
100 % CWE-203 Information Exposure Through Discrepancy

CPE : Common Platform Enumeration

TypeDescriptionCount
Application 1
Os 3466

Sources (Detail)

https://git.kernel.org/stable/c/002665dcba4bbec8c82f0aeb4bd3f44334ed2c14
https://git.kernel.org/stable/c/a7748e021b9fb7739e3cb88449296539de0b6817
https://git.kernel.org/stable/c/d8778e393afa421f1f117471144f8ce6deb6953a
Source Url

Alert History

If you want to see full details history, please login or register.
0
1
2
3
4
5
6
7
Date Informations
2025-07-15 01:53:19
  • Multiple Updates
2025-07-14 12:16:55
  • Multiple Updates
2025-06-26 01:52:10
  • Multiple Updates
2025-06-25 12:16:22
  • Multiple Updates
2025-06-24 01:56:38
  • Multiple Updates
2025-05-27 01:49:42
  • Multiple Updates
2024-11-25 09:25:28
  • Multiple Updates
2024-05-21 21:27:27
  • First insertion